
SanDisk Industrial Grade CompactFlash 5000 Product Manual
© 2007 SanDisk® Corporation 25 July 2007
3) D[15::0] signifies data provided by the host system to the
CompactFlash Memory Card.
Table 20 contains the specification information related to the I/O Write Timing
Diagram.
Table 20: I/O Write Timing Specification
Item Symbol IEEE Symbol Min. (ns) Max. (ns)
Data Setup before -IOWR tsu (IOWR) tDVIWL 60
Data Hold following -IOWR th (IOWR) tWHDX 30
-IOWR Width Time tw (IOWR) tlWLIWH 165
Address Setup before -IOWR tsuA(IOWR) tAVIWL 70
Address Hold following -IOWR thA(IOWR) tlWHAX 20
-CE Setup before -IOWR tsuCE(IOWR) tELIWL 5
-CE Hold following -IOWR thCE(IOWR) tlWHEH 20
-REG Setup before -IOWR tsuREG(IOWR) tRGLIWL 5
-REG Hold following -IOWR thREG(IOWR) tlWHRGH 0
-IOIS16 Delay falling from Address tdfIOIS16(ADR) tAVISL 35
a
-IOIS16 Delay rising from -IORD tdr-
IOIS16(ADR)
tAVISH 35
-IOIS16 Delay falling from Address tdfIOIS16(ADR) tAVISL 35
-IOIS16 Delay rising from Address tdrIOIS16(ADR) tAVISH 35
a The maximum load on -IOIS16 is 1 LSTTL with 50 pF total load.
3.3.10
True IDE Mode
The following sections provide valuable information on the True IDE mode.
De-skewing
The host will provide cable de-skewing for all signals originating from the
device. The device will provide cable de-skewing for all signals originating from
the host.
All timing values and diagrams are shown and measured at the connector of
the selected device.
Transfer Timing
The minimum cycle time supported by devices in PIO Mode 3, 4 and Multiword
DMA Mode 1, 2 respectively will always be greater than or equal to the
minimum cycle time defined by the associated mode (e.g., a device supporting
PIO Mode 4 timing will not report a value less than 120 ns, the minimum cycle
time defined for PIO mode 4 timings).
Register Transfers
Figure 9 defines the relationships between the interface signals for register
transfers. For PIO Modes 3 and above, the minimum value of t
0
is specified by
Word 68 in the IDENTIFY DEVICE parameter list. Table 22 defines the
minimum value that will be placed in Word 68. In Figure 9 all signals are
shown with the asserted condition facing the top of the page. The negated
condition is shown towards the bottom of the page relative to the asserted
condition.
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