SanDisk SD032 Manual descargar pdf (Pagina 81)

4.11.2. Data Read

Note that the DAT line represents the data bus (either 1 or 4 bits).

Single Block Read

The host selects one card for data read operation by CMD7, and sets the valid block length for block oriented data

transfer by CMD16. The basic bus timing for a read operation is given in Figure 5-17. The sequence starts with a

single block read command (CMD17) which specifies the start address in the argument field. The response is sent

on the CMD line as usual.

<----- Host command -----> <-N

cycles-> <-------- Response --------->

CMD S T content CRC E Z Z P * * * P S T content CRC E

<------- N

cycles -------> <- Read Data

DAT Z Z Z * * * * Z Z Z Z Z Z P * * * * * * * * P S D D D * * *

Figure 4-17. Timing of Single Block Read

Data transmission from the card starts after the access time delay N

beginning from the end bit of the read

command. After the last data bit, the CRC check bits are suffixed to allow the host to check for transmission errors.

Multiple Block Read

In multiple block read mode, the card sends a continuous flow of data blocks following the initial host read

command. The data flow is terminated by a stop transmission command (CMD12). Figure 4-18 describes the timing

of the data blocks and Figure 4- describes the response to a stop command. The data transmission stops two clock

cycles after the end bit of the stop command.

<-- Host command ---> <-N

cycles-> <---- Response ------>

CMD S T content CRC E Z Z P * P S T content CRC E Z Z P P P P P P P P P P P P P

<--- N

cycles ----> <-- Read Data --> <- N

cycles -> <- Read Data ->

DAT Z Z Z * * * Z Z Z Z Z Z P * * * * * * P S content CRC E P * * * * * * P S D D D D D

Figure 4-18. Timing of Multiple Block Read Command

<----- Host command -----> <-N

cycles-> <-------- Response --------->

CMD S T content CRC E Z Z P * * * P S T content CRC E

DAT D D D * * * * * * * D D D E Z Z * * * * * * * * * * * * * * * * * *

Figure 4-19. Timing of Stop Command (CMD12, Data Transfer Mode)

4.11.3. Data Write

Single Block Write

The host selects one card for data write operation by CMD7. The host sets the valid block length for block-oriented

data transfer by CMD16.

The basic bus timing for a write operation is given in Figure 5-20. The sequence starts with a single block write

command (CMD24) that determines (in the argument field) the start address. It is responded by the card on the

CMD line as usual. The data transfer from the host starts N

clock cycles after the card response was received.

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SanDisk SD032 Manual Pagina 81